project new /home/cc/cs150/sp13/class/cs150-ax/dviproj/pcores/vgain_v1_00_a/devl/projnav/vgain.xise;
project set family virtex5;
project set device xc5vlx110t;
project set package ff1136;
project set speed -1;
project set top_level_module_type HDL;
project set synthesis_tool "XST (VHDL/Verilog)";
lib_vhdl new vgain_v1_00_a;
xfile add /home/cc/cs150/sp13/class/cs150-ax/dviproj//pcores/vgain_v1_00_a/hdl/verilog/vgain.v;
project close;
